FOUNDRY
- ELENA’s ambition is to establish the first European open-access LNOI PIC foundry. The entire ELENA consortium is working towards this goal.
- The CONSORTIUM page informs you about the role of each partner and how ELENA’s activities come together.
- In the meantime, ELENA’s coordinator CSEM offers a pre-commercial foundry service for LNOI PICs, serving prototyping and R&D projects. Access is open to the entire photonics industry and academic researchers worldwide. CSEM already exported LNOI chips to Europe, North America, Asia and Australia, and the ELENA consortium is looking forward to expand the LNOI PIC end-user group worldwide. Through this service, PIC designers not only get access to ELENA’s current LNOI process design kit (PDK), but also have the flexibility to devise customised components and circuits that comply with the fabrication design rules.
Current offerings
| MPW RUNS | Multiple RUNs/year * (see the MPW schedule table below) | Multiple RUNs/year * (see the MPW schedule table below) | Custom chip size from 5×5 mm2 up to 10×30 mm2 ** |
* Envisioned to ramp up to four RUNs per year during ELENA
** ELENA envisions to reduce chip size down to 2.5 x 2.5 mm2
MWP / MULTI-PROJECT WAFER SERVICE
Multi-Project Wafer (MPW) RUNs
Our pre-commercial MPW RUNs enable researchers to access the novel LNOI PIC platform at affordable cost, lowering the barrier for the industry to adopt the new technology. This fabless access to the LNOI platform allows designers to leverage the extensive library of standardised building blocks as a part of the PDK which is being developed within ELENA.
Schedule of the MPW RUNs
| MPW RUN ID | Design Submission Deadline | Expected Shipping Date | Status |
|---|---|---|---|
| ELENA_LNOI_2022_RUN1 | 15/04/2022 | 31/10/2022 | Delivered |
| ELENA_LNOI_2022_RUN2 | 15/11/2022 | 31/03/2023 | Delivered |
| ELENA_LNOI_2023_RUN3 | 15/02/2023 | 31/08/2023 | Ongoing |
| ELENA_LNOI_2023_RUN4 | 31/08/2023 | 30/04/2024 | Accepting designs |
How Clients Interact with the LNOI PIC Foundry Service
Access to PDK: After signing an NDA, we provide you with a preliminary PDK which includes the detailed technology layer stack and design rules, the most updated version of the building block geometry and performance results, as well as the physical models for circuit simulations in the software developed by ELENA partner VPI Photonics. Contact us to get access to our LNOI PIC PDK.
Design submission: Once you have obtained access to the PDK, you will need to register for an MPW RUN and fix the required area for your design. The clients will receive a quotation based on the reserved area. The designs have to be submitted in .gds format by the client. The designs can be generated in any given design software such as Nazca, IPKISs, L-Edit, Optodesigner, etc.
CSEM closely engages with the clients during the tape-out phase, not only by providing functional advice, but also by making sure that the final designs are compatible with the DRC.
Floorplan/DRC: The CSEM team will take care of the final floorplan and DRC just before the fabrication. In this phase, your design will be locked for any further amendments. However, we might come back to you if we notice a high-level design rule violation when placing your design in the final mask plan.
Fabrication: After the final floor plan and DRCs, the fabrication process starts. No amendment in your design is applicable in this phase. You will be engaged with the CSEM team to get updates on the progress, including on-demand optical and SEM inspection images.
Chip shipment: The fabrication process finishes with a set of standard cleaning procedures. You will receive fully cleaned chips, ready for characterization. The chips are shipped to you as soon as fabrication is completed.
